Integrated circuit logic states are maintained by virtue of specific transistor combinations being either conducting or nonconducting. High energy ion strikes on the microcircuit generate photocurrents whose primary detrimental effect is to make transistors in the nonconducting or OFF state appear to be conducting or ON, thereby confusing the logic state and leading to single event upset (SEU). Protection against these soft errors is accomplished using either technology or circuit techniques, both of which generally impact yield and performance relative to unhardened circuits. Effective SEU hardening is accomplished generically in three ways: (1) error correction; (2) circuit techniques; and (3) technology modifications.
Error correction techniques are logic operations which are spatially removed from the latch, either on or off chip. The most popular technique is the Hamming code as in J. S. Pridmore, "Designing Hardened CMOS/SOS Circuits", PROCEEDINGS OF THE IEEE, Vol. 76, 1483 (1988), where seven bits are needed to correct four bits. Thus, an area penalty of about thirty percent on the chip and a speed penalty of about fifty percent are imposed when the error correction technique is used.
Circuit techniques are generally designed to stiffen the struck node and prevent node transients or prevent their propagation within the latch. A typical example is given by L. R. Rockett, "An SEU-Hardened CMOS Data Latch Design", IEEE TRANS. NUCL. SCI., NS-35, 1682 (1988), and in L. R. Rockett, "Designing Hardened Bulk/Epi CMOS Circuits", PROCEEDINGS OF THE IEEE, 1474 (1988), which papers demonstrate this type protection. Although significant practical improvement results from these circuit techniques, the circuit is not completely hardened because a sufficiently large ion strike may actually upset the cell.
Examples of technology modification techniques to accomplish SEU hardening have been discussed in Weaver et. al., "An SEU Tolerant Memory Cell Derived from Fundamental Studies of SEU Mechanisms in SRAM", IEEE TRANS. NUCL. SCI., NS-34, 1281 (1987). Resistors are placed in the memory cell "write" path to slow the cell response to allow circuit recovery before the upset signal is latched in. Designing the memory cell so that the write time is longer than the ion-induced photocurrent transients eliminates spurious writing, thereby inhibiting SEU. Alternatively, resistors may be placed in the drain lines to divide the voltage transients at feedback points resulting for strikes on the p-channel transistors. Properly choosing these drain resistors can completely protect the unstruck inverter by never allowing the gate voltage to be sufficient to switch. Ion induced transients that pose a threat to logic occur primarily at the drains of OFF transistors because photocurrents are always directed to reinforce the ON transistor node voltage. There is one exception to this condition that occurs when an ON transistor is located in a well or tub, i.e., n-channel transistor of a p-well technology. In this case, upsets can be produced with very high energy ions, but the probability of such an occurrence is rare and often neglected. Although addition of diodes has been proposed to harden cells, the only effective technology thus far is the use of resistors. There are many practical problems to the technology approach and there is some question about its viability at very high integration levels. Speed is affected and total immunity is not always possible. Testing of the individual cells is also not possible. Examples of these techniques are set forth in U.S. Pat. No. 4,914,629 entitled "Memory Cell Including Single Event Upset Rate Reduction Circuitry," to Blake et al., Apr. 3, 1990; and in U.S. Pat. No. 4,956,814, entitled "Memory Cell with Improved Single Event Upset Rate Reduction Circuitry," to Houston, Sep. 11, 1990.
One resistor technique in U.S. Pat. No. 4,809,226, entitled "Random Access Memory Immune to Single Event Upset Using a T-Resistor," to Ochoa, Feb. 28, 1989, and in Ochoa et al., "A Proposed New Structure for SEU Immunity in SRAM Employing Drain Resistance", IEEE ELEC. DEV. LETT., ELD-8, 537 (1987), uses much smaller resistors than conventionally connected between inverters. Ochoa uses resistors to protect the most sensitive node, i.e., the drain of the OFF p-channel transistor is protected by placing a resistor between it and the information node. However, to completely protect against ion strikes on transistors within wells, a second set of resistors is required.
It is thus an object of the invention to provide a memory latch with an asymmetric response to an SEU resulting from an ion strike. This object is achieved with the implementation of two cross-coupled inverters, wherein the coupling or feedback node of each inverter is electrically connected to the gate of the other inverter, and wherein a voltage dividing device is placed between the p-channel and the n-channel transistors of each inverter. An advantage of this arrangement is that because one logic state is hardened, ion strikes affect only the other logic state. Thus, the invention protects one logic state while allowing SEU when in the other state, thereby providing an asymmetric response. The use of these impedance elements is a fundamentally different use of prior art voltage division mechanisms.
It is yet another object of the invention to provide for complete immunity from SEU in a memory cell. This object is achieved by the implementation of asymmetric latches having one hardened logic state as stated above in a parallel configuration to provide for redundancy. Thus, the logic state of each latch can be interrogated, and with an AND gate, upsets can be corrected.
It is yet another object of the invention to provide for a memory cell completely immune from SEU without significant loss in memory speed and with minor loss in available chip area. This object is achieved by the parallel implementation of a fast asymmetric response memory latch.
The invention comprises a memory cell design that is completely immune to single event upset. It employs enhancement mode MOSFET transistors and either depletion mode MOSFET or resistors. The cell exhibits no loss in speed relative to a normal six transistor static RAM cell. In contrast to the circuit techniques, the invention herein does not attempt to prevent a single latch upset, but corrects the upset "in place" with the control latches. In this sense, our cell can not be upset even with very long transients. Also the usual circuit hardening approach requires speed penalties, in contrast to our parallel connections.